Research Area
Equivalent transformations and partitioning graph-schemes of parallel logical control algorithms in the annex to the design of logic control systems.
Current scientific goal
Analysis of the quality of graph partitioning schemes of parallel logical control algorithms by different heuristic methods.
Project Description
Logic control system (SLN) has recently become more widespread due to the increasing use of automated robotic assembly lines capable of carrying out the necessary operations with little or no human intervention (or reducing such involvement to a minimum), on the one hand, and the success of microelectronics, steadily following Moore's Law , on the other.
The main applications of such systems are:
- The systems of this class of special requirements of high performance, resiliency and, if possible, low hardware complexity (because of its influence on the mass and size parameters) and cost.
- Management robotic conveyor lines or machines with numerical control, which essentially reduce to the management of inertial actuators do not require high performance: the fore the yield criteria of low cost and possibility of rapid reconfiguration when the SDE of the operations performed (the introduction of new equipment, changing the composition of products, etc.).
- Management of electronic devices (processors, accelerators, specialized calculators, etc.), the frequency of which can reach several gigahertz. In this light, to such control systems are primarily special requirements of high speed and low cost, partly due to a moderate hardware complexity.
- Management robotic conveyor lines or machines with numerical control, which essentially reduce to the management of inertial actuators do not require high performance: the fore the yield criteria of low cost and possibility of rapid reconfiguration when the SDE of the operations performed (the introduction of new equipment, changing the composition of products, etc.).
February 2015
We are starting new scientific experiment aimed to trying to use returning strategy with well known heuristic methods (greedy (g), random search (rmr), weighted random search (wrmr)) and new implementations for simulated annealing method (sa) and limited depth first search (ldfs) at the problem of getting shortest pathes in given graph.
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 Gerasim@home
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| Start |
2007
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| End |
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| Status |
Alpha
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| Admin |
SerVal
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| Institution |
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| Country |
Russia
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| Area |
Mathematics
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 Apps
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 Win |
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 Linux |
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 Mac |
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 64bit |
spstarter 2.92 [win]
Test Separator 1.15 [win]
ODLS BS 1.03 [win]
Graph Coloring 1.00 [win]
Get Decic Fields 4.00 [win]
Hugo Search 1.00 [win]
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 PS3 |
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 ATI |
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 CUDA |
Get Decic Fields 4.02 [win]
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 Intel |
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 Android |
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 RPi |
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 NCI |
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 System-Specs
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| VRAM |
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SP |
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DP |
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| RAM |
5MB
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| Runtime |
15-45min
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| HDD |
2,7MB
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| Traffic dl/ul |
kb / kb
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| Deadline |
10 days
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| Checkpoints |
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